The invention relates generally to semiconductor structures and the fabrication of semiconductor chips and, in particular, to pillar-type connections and methods for fabricating pillar-type connections during the back-end-of-line processing of semiconductor chips.
A chip or die includes integrated circuits formed by front-end-of-line processing using the semiconductor material of a wafer, a local interconnect level formed by middle-end-of-line processing, and stacked metallization levels of an interconnect structure formed by back-end-of line processing. After singulation from the wafer, chips may be packaged using a controlled collapse chip connection or flip chip process. Solder bumps provide mechanical and electrical connections between bond pads in the last or top metallization level and the package. The solder bumps establish physical attachment and electrical contact between an the bond pads and a complementary array of bond pads on a package.
Conductive pillars are a next generation flip chip interconnect technology that is competitive with solder bumps. Fine-pitch conductive pillars are capable of providing improved thermal and electrical performance, compared to solder interconnects, in smaller geometries and at tighter pitches. In addition, conductive pillars reduce the amount of solder required to form the mechanical and electrical connections between bond pads in the top metallization level and the package.
Improved pillar-type connections and methods for fabricating pillar-type connections are needed.